This is not easy! Transistor Q5 is strapped across RV3a and is itself controlled by RV3b. The Attack pot of Channel I also provides for very long Attack times for fade-in and is required to operate over six decades of current while maintaining a sensible knob calibration. The Release pot must control a range of three and a half decades of current, while maintaining a sensible knob calibration and the current mirror circuit enables a conventional pot, of modest value, to be used. Hence the use of a constant current charging circuit. For the Attack phase an exponential change of voltage on CI4 with time is appropriate, but it is unacceptable for long Release times, manifesting itself as a sudden drop in volume followed by a slower decay. CI4 is then charged up linearly by the current mirror circuit of Q3 and Q4, the actual charging current being set by Release pot RV4. When both the Hold circuit and the trigger line SCH go low, Q2 and IC6c are turned hard off, switch IC6d is turned on and the side chain enters the Release phase. For slower Attack times the rate of discharge is set by Attack pot RV3a. CMOS switch IC6c is paralleled with Q2 to ensure that this happens, otherwise the Vce voltage of Q2 would remain on CI4. It is important in connection with the dbx VCA employed that CI4 discharges completely to zero volts. This is the reason for paralleling ICSb and c and also for speed-up capacitor CI3. In order to achieve a minimum Attack time often microseconds (RV3 at zero ohms), it is necessary to inject a large pulse of base current into Q2. When either of these is high the output of IC5a goes low, turning off the Release CMOS switch IC6d and causes the combined outputs of ICSb and c to go high, turning on Q2 and discharging the main time constant capacitor CI4. The output of the Hold circuit and the trigger line SCH are summed in NOR gate IC5a. Only when the voltage on CI2 exceeds 13.6 volts does the output of comparator IC7a go low as long as it is high the side chain is held in the Attack phase. CI2 then charges back up at a rate set by Hold time pot RV2. When the triggering signal once more falls below threshold and SCH line goes low, inverter IC5d goes high turning on CMOS switch IC6a. When trigger line SCH goes high, Ql is turned on and the Hold capacitor CI2 is discharged in about two microseconds. On the PCB the side chain ground is kept completely separate from the signal ground! In order to achieve extremely fast minimum attack times it is necessary to discharge time constant capacitor CI4, rather than try to charge it up, since momentary currents in the order of I amp are indicated, which would place an impossible burden on the power supply. Such gates cannot open as fast as their manufacturers claim!). Trigger line SCH is fed simultaneously both to the Hold t and to the Attack circuitry (some manufacturers put these two sections in series so that the Attack phase cannot be initiated until the Hold Circuit has been set. In the absence of a positive voltage from IC4c the trigger line SCH is held low by R37. Diodes D6 and D7 form an OR gate allowing the unit to be triggered also from the Manual button SW4. If the input signal exceeds the selected threshold the output of IC4c goes momentarily positive, triggering the Attack phase (note that diode D5 prevents it going negative). The rectified signal is compared with a DC voltage from the Threshold pot RVI by comparator IC4c. This is in order to spread out the calibration of the Threshold control, otherwise the - lOdBm to -HOdBm range would be crammed up at one end of the knob. Network R26, R27, Dl and D2 provides compression of the rectified signal at high levels. Whichever signal is selected is fed to a precision full-wave rectifier built around IC4a and d. "Key switch SW3 selects Internal or External triggering. This is the sort of thing: (for something else entirely)
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